Unknown
Cooper Lake (microprocessor)
2020
desktop
Microarchitecture
Skylake
Historical hardware entry sourced from Wikipedia: Cooper Lake (microprocessor).
Key specifications
- Cores
- 16 / threads
- Clock
- 4.3
- Socket
- LGA 4189
general
| 10 nm | Tremont |
|---|---|
| 130 nm | Tualatin |
| 14 nm | Airmont |
| 180 nm | Coppermine |
| 22 nm | Silvermont |
| 250 nm | Deschutes |
| 32 nm | Saltwell |
| 350 nm | Pentium Pro(166–200 MHz) |
| 45 nm | Bonnell |
| 500 nm | Pentium Pro(150 MHz) |
| 65 nm | Yonah |
| 90 nm | Dothan |
| Application | 4S and 8S servers |
| Brand name | Xeon |
| Common manufacturer | Intel |
| Designed by | Intel |
| Extensions | AES-NI, CLMUL, RDRAND, TXT, FSGSBASE, MOVBE, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, MPX, TSX, VT-x, VT-d |
| Instruction set | x86-64 |
| Instructions | MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, bfloat16 |
| Intel 18A | Arctic Wolf |
| Intel 3 | Arrow Lake-U |
| Intel 4 | Crestmont |
| Intel 7(10 nm ESF) | Gracemont |
| L1 cache | 64 KB per core (32 instructions + 32 data) |
| L2 cache | 1 MB per core |
| L3 cache | Up to 38.5 MB (1.375 MB/core) |
| Launched | June 18, 2020; 5 years ago (June 18, 2020) |
| Marketed by | Intel |
| Microarchitecture | Skylake |
| Model | Cooper Lake-SP |
| N3B (TSMC) | Skymont |
| NetBurst | Katmai |
| NetBurst(HT) | Pentium M |
| Predecessor | Cascade Lake |
| Product code name | CPL |
| Socket | LGA 4189 |
| Successors | Same generation Ice Lake (10nm, For 1S and 2S systems) Next generation Sapphire Rapids |
| Technology node | 14 nm (Tri-Gate) transistors |
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Sources
- WIKIPEDIA_PROCESSORS · 2 days ago
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